In previous blog posts I’ve mentioned some terms like “65xx ISA” and “Addressable Register Architecture (ARA).” I suspect most software engineers have conceptual knowledge of instruction sets and their classification. As an example, the x86 instruction set is much more complex than the reduced instruction set of the ARM. This is where the terms CISC and RISC get thrown around and most conversations end. I felt compelled to do more research to deepen my conceptual knowledge and find out where ARA fits in the landscape of ISAs. That’s my goal of this post. If you’re looking for something more in-depth then you’ll likely have to keep looking but check out the Fun Facts before you go. A special thanks to my uncle Bill Mensch for providing information on ARA and tolerating my basic knowledge questions.
In order for me to understand ARA, I needed to get a better understanding of ISA. So, like most, I looked to the internet. I was not setting out to do a “deep dive” but just to gather enough information to get some context. The “aha” moment for me came when I discovered the separation between the ISA and the underlying microarchitecture of a microprocessor. A microarchitecture is a given way to implement an Instruction Set Architecture. I immediately saw similarities in the relationship between the Java Virtual Machine (JVM) specification and runtime being analogous to an ISA and microarchitecture. Oracle maintains JVM specifications (e.g. Java SE 7) that can be thought of like an Instruction Set Architecture. As most software engineers know, Oracle also offers a implementation (or runtime) of the JVM specification similar to how a microarchitecture implements an ISA. There are 40+ implementations of the JVM specification including the Dalvik and ART JVMs that make up the Android runtime. So, now it was clear to me the role of an ISA and I can start pestering uncle Billy about ARA.🙂
Bill told me that he coined the term Addressable Register Architecture (ARA) about 5 years ago to describe the 65xx ISA. According to him, “…there had to be an essential architectural advantage to explain the extremely wide and successful application of the 6502 and it’s decedents (W65C02, W65C02S & W65C816)“. Bill explains his realization to me in an email:
…I realized that the wider data widths such as 64-bit floating point operations might be the key. So it was always related to by Motorola and others as “memory mapped IO” but no one actually looked at the fact that the floating point registers were in “page Zero” and could have been anywhere in memory. Page Zero was selected because it uses less machine cycles. Using a C compiler, other registers are stored in memory. Actually, all IO registers are “addressed” and that is how I arrived at defining the 65xx as an ARA. – Bill Mensch, Oct 2015
ARA gives 65xx ISA a unique identity which is neither CISC nor RISC. So, in my “layman’s world” I think of ARA as an ISA that is the “best of both worlds” sitting nicely in between CISC & RISC. This is where I leave you to continue exploring and digging deeper if you desire. This is a fascinating world that is extremely complex.
Before you leave, take a look at the Fun Facts, I think you’ll be surprised!
Fun Fact #1: Did you know that a microarchitecture has more affect on power, energy and/or performance than instruction set architectures, e.g. CISC or RISC? Here’s a great EETimes blog post (RISC vs CISC: What’s the Difference?) that reveals this finding of a 4 year study from the Vertical Research Group.
Fun Fact #2: “The ARM engineers Steve Furber and Sophie (then Roger) Wilson visited me in my WDC Mesa offices the November-December time frame in 1983 asking me to design a 32-bit microprocessor which could have been best described as a RISC processor. They were partially funded by Apple for around $3M and Apple used the Acorn RISC Machine (ARM) in the failed Newton PDA. Acorn RISC Machine became Advanced RISC Machine and in an attempt to get away from the RISC identity became just ARM.” – Bill Mensch, June 2015
…Bill respectfully declined to design the 32-bit microprocessor for the ARM engineers.
Fun Fact #3: The 6502 made an appearance in the first Terminator movie! The T-800 HUD (Head Up Display) features 6502 assembly code. It was determined to be Apple-II code taken from Nibble Magazine. (http://www.pagetable.com/?p=64) The feature image is from the T-800 HUD.